1. Field
The present disclosure generally relates to clocking circuits. More specifically, the present disclosure relates to an at-rate clock-data-recovery (CDR) circuit that recovers a clock signal with a pulse-response precursor h(−1) converged to a non-zero value.
2. Related Art
Clock-data-recovery (CDR) circuits are widely used in serializer/deserializer (SerDes) receiver circuits. These CDR circuits typically use one of two CDR techniques to recover a clock signal from received data. In a first CDR technique (which is sometimes referred to as ‘bang-bang CDR’), both data and edge samples are used to extract timing information (either early or late). Thus, the rate of the resulting clock signal is double that of the data rate.
In contrast, the second CDR technique (which is sometimes referred to as ‘Muller-Mueller CDR’) does not use edge samples; it only uses data samples. Therefore, the rate of the resulting clock signal is the same as the data rate (i.e., the second CDR technique provides at-rate CDR). By avoiding a double-rate clock, the second CDR technique significantly reduces the power consumption.
In existing implementations of the second CDR technique, the CDR convergence condition is to force the last pulse-response precursor h(−1) (which is adjacent to the pulse-response cursor h(0)) to equal the first pulse-response postcursor h(1) (which is also adjacent to the pulse-response cursor h(0)), so that a symmetric pulse response can be obtained. Because h(1) is typically compensated by equalization (such as a linear equalizer or a decision-feedback equalizer), h(1) is often close to zero. Therefore, CDR convergence in this CDR technique usually requires h(−1) to equal zero. For a long communication channel, where precursor intersymbol interference is high, it may be necessary to compensate h(−1), for example, using precompensation in a transmitter circuit or with a feed-forward equalizer in the receiver circuit. However, if the communication channel is very long and/or if the data rate is very high, the precompensation or feed-forward equalization needed to maintain the CDR locking condition may be very large.
Furthermore, when the precompensation is increased, the magnitude of the pulse-response cursor h(0) and, thus, the voltage margin are reduced (i.e., the error rate is typically increased). In addition, a large amount of precompensation may introduce considerable errors in a second pulse-response precursor h(−2). However, applying a correction to h(−2) may further reduce the magnitude of the pulse-response cursor h(0). This recursive effect may even result in an error at a third pulse-response precursor h(−3).
Hence, what is needed is a CDR circuit without the above-described problems.